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SIP41105
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Vishay Siliconix
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Half-Bridge N-Channel MOSFET Driver for DC/DC Conversion
FEATURES
D D D D D D D D D 5-V Gate Drive Undervoltage Lockout Internal Bootstrap Diode Adaptive Shoot-Through Protection Syncronous MOSFET Enable Shutdown Control Adjustable HighsidePropagation Delay Switching Frequency Up to 1 MHz Drive MOSFETs In 4.5- to 50-V Systems
APPLICATIONS
D D D D D D Multi-Phase DC/DC Conversion High Current Synchronous Buck Converters High Frequency Synchronous Buck Converters Asynchronous-to-Synchronous Adaptations Mobile Computer DC/DC Converters Desktop Computer DC/DC Converters
DESCRIPTION
SIP41105 is a high-speed half-bridge MOSFET driver with adaptive shoot-through protection for use in high frequency, high current, multiphase dc-dc synchronous rectifier buck power supplies. It is designed to operate at switching frequencies up to 1 MHz. The high-side driver is bootstrapped to allow driving n-channel MOSFETs. SIP41105 comes with adaptive shoot-through protection to prevent simultaneous conduction of the external MOSFETs. The SIP41105 is available in a 16-Pin TSSOP PowerPAKr package and is specified to operate over the industrial temperature range of -40 _C to 85 _C.
FUNCTIONAL BLOCK DIAGRAM
+5 to 50 V +5 V
DELAY
VDD
BOOT
OUTH
SIP41105
SD Controller PWM ENSYNC LX VOUT
OUTL
AGND
PGND
GND
GND
Document Number: 72719 S-50265--Rev. C, 21-Feb-05
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SIP41105
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ABSOLUTE MAXIMUM RATINGS (ALL VOLTAGES REFERENCED TO GND = 0 V)
VDD, PWM, SD, ENSYNC, DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V LX, BOOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 V BOOT to LX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 to 150_C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125_C Power Dissipationa TSSOP-16 PowerPAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6 W Thermal Impedance (QJA)a TSSOP-16 PowerPAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38_C/W Notes a. Device mounted with all leads soldered or welded to PC board. a. Derate 26.3 mW/_C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING RANGE (ALL VOLTAGES REFERENCED TO GND = 0 V)
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 V to 5.5 V VBOOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 V to 50 V CBOOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 nF to 1 mF Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 to 85_C
SPECIFICATIONSa
Test Conditions Unless Specified Parameter Power Supplies
Supply Voltage Quiescent Current Shutdown Current VDD IDDQ ISD fPWM = 1 MHz, CLOAD = 0 SD = Low 4.5 2.4 5.5 3.0 1 V mA mA
Limits Mina Typb Maxa Unit
Symbol
VDD = 5 V, VBOOT - VLX = 5 V, CLOAD = 3 nF TA = -40 to 85_C
Reference Voltage
Break-Before-Makec VBBM 1 V
PWM Input
Input High Input Low Bias Current VIH VIL IB VIH VIL ENSYNC SD IB SD = 5 V 3.5 2.0 "0.3 4.0 VDD 0.5 "1 V mA
SD, ENSYNC Inputs
Input High Input Low Bias Current VDD 1.0 "1 7 V mA
High-Side Undervoltage Lockout
Threshold VUVHS Rising or Falling 2.5 3.35 3.75 V
Bootstrap Diode
Forward Voltage VF IF = 10 mA, TA = 25_C 0.70 0.76 0.82 V
MOSFET Drivers
High-Side Drive Currentc Low-Side Drive Currentc High-Side High Side Driver Impedance Low-Side Low Side Driver Impedance IPKH(source) IPKH(sink) IPKL(source) IPKL(sink) RDH(source) RDH(sink) RDL(source) RDL(sink) 0.9 1.1 0.8 1.5 2.5 2.2 3.4 1.4 3.8 3.3 5.1 2.1 W A
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Document Number: 72719 S-50265--Rev. C, 21-Feb-05
SIP41105
New Product
SPECIFICATIONSa
Test Conditions Unless Specified Parameter MOSFET Drivers
High-Side Rise Time High-Side Fall Time High-Side High Side Propagation Delayc Low-Side Rise Time Low-Side Fall Time Low-Side Low Side Propagation Delayc trH tfH td(off)H td(on)H trL tfL td(off)L td(on)L 10% - 90% 90% - 10% See Timing Waveforms See Timing Waveforms 10% - 90% 90% - 10% See Timing Waveforms See Timing Waveforms 32 36 20 30 45 20 30 30 55 30 ns 40 45
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Limits Mina Typb Maxa Unit
Symbol
VDD = 5 V, VBOOT - VLX = 5 V, CLOAD = 3 nF TA = -40 to 85_C
LX Timer
LX Falling Timeoutc tLX 420 ns
VDD Undervoltage Lockout
Threshold Rising Threshold Falling Hysteresis Power on Reset Timec VUVLOR VUVLOF 3.7 4.3 4.1 0.4 2.5 ms 4.5 V
Thermal Shutdown
Temperature Hysteresis TSD TH Temperature Rising Temperature Falling 165 25 _C
Notes a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum (-40_ to 85_C). b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing and are measured at VCC = 5V unless otherwise noted. c. Guaranteed by design. Add 1.2 ns/pF to td(on)H with external capacitor.
TIMING WAVEFORMS
PWM 50% 90% 10% tfH 90% OUTL td(off)H 10% 90% 10% td(on)H 10% trH 50% 90%
OUTH
trL td(off)L
tfL
LX 1V
td(on)L
Document Number: 72719 S-50265--Rev. C, 21-Feb-05
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SIP41105
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PIN CONFIGURATION AND TRUTH TABLE
TSSOP-16 PowerPAK
NC OUTH BOOT SD PWM DELAY AGND PGND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 NC LX ENSYNC NC NC VDD OUTL NC
TRUTH TABLE
PWM
L H L H X
SD
H H H H L
ENSYNC
L L H H X
OUTH
L H L H L
OUTL
L L H L L
ORDERING INFORMATION
Part Number
SIP41105DQP-T1
Temperature Range
-40 to 85_C
Marking
41105
Eval Kit
SIP41105DB
Temperature Range
-40 to 85_C
PIN DESCRIPTION
Pin Number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Name
NC OUTH BOOT SD PWM DELAY AGND PGND NC OUTL VDD NC NC ENSYNC LX NC No Connection High-side MOSFET gate drive
Function
Bootstrap supply for high-side driver. A capacitor connects between BOOT and LX. Shuts down the driver IC Input signal for the MOSFET drivers Connection for the highside delay adjustment capacitor. Analog Ground Power Ground No Connection Synchronous or low-side MOSFET gate drive +5-V supply No Connection No Connection Enables OUTL, the driver for the synchronus MOSFET Connection to source of high-side MOSFET, drain of the low-side MOSFET, and the inductor No Connection
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Document Number: 72719 S-50265--Rev. C, 21-Feb-05
SIP41105
New Product
FUNCTIONAL BLOCK DIAGRAM
Vishay Siliconix
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VDD
BOOT
SD
UVLO OTP
OUTH
LX DELAY DELAY PWM ENSYNC VDD OUTL - + VBBM
GND
Figure 1.
DETAILED OPERATION
PWM The PWM pin controls the switching of the external MOSFETs. The driver logic operates in a noninverting configuration. The PWM input stage should be driven by a signal with fast transition times, like those provided by a PWM controller or logic gate, (<200 ns). The PWM input functions as a logic input and is not intended for applications where a slow changing input voltage is used to generate a switching output when the input switching threshold voltage is reached. Low-Side Driver The supplies for the low-side driver are VDD and GND. During shutdown, OUTL is held low. High-Side Driver The high-side driver is isolated from the substrate to create a floating high-side driver so that an n-channel MOSFET can be used for the high-side switch. The supplies for the high-side driver are BOOT and LX. The voltage is supplied by a floating bootstrap capacitor, which is continually recharged by the switching action of the output. During shutdown OUTH is held low. Bootstrap Circuit The internal bootstrap diode and a bootstrap capacitor form a charge pump that supplies voltage to the BOOT pin. An
Document Number: 72719 S-50265--Rev. C, 21-Feb-05
integrated bootstrap diode replaces the external Schottky diode needed for the bootstrap circuit; only a capacitor is necessary to complete the bootstrap circuit. The bootstrap capacitor is sized according to,
CBOOT = (QGATE/DVBOOT - LX) x 10
where QGATE is the gate charge needed to turn on the high-side MOSFET and DVBOOT - LX is the amount of droop allowed in the bootstrapped supply voltage when the high-side MOSFET is driven high. The bootstrap capacitor value is typically 0.1 mF to 1 mF. The bootstrap capacitor voltage rating must be greater than VDD + 5 V to withstand transient spikes and ringing. Shoot-Through Protection The external MOSFETs are prevented from conducting at the same time during transitions. Break-before-make circuits monitor the voltages on the LX pin and the OUTL pin and control the switching as follows: When the signal on PWM goes low, OUTH will go low after an internal propagation delay. After the voltage on LX falls below 1 V by the inductor action, the low-side driver is enabled and OUTL goes high after some delay. When the signal on PWM goes high, OUTL will go low after an internal propagation delay. After the voltage on OUTL drops below 1 V the high-side driver is enabled and OUTH will go high after an internal propagation delay. If LX does not drop below 1 V within 400 ns after OUTH goes low, OUTL is forced high until the next PWM transition.
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SIP41105
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Delay The addition of a capacitor between DELAY and GND will increase the propagation delay time for OUTH going high. Delay capacitance may be added to prevent shoot through current in the low-side MOSFET due to the finite time between OUTL going low and the continuing conduction of the low-side MOSFET. Choose a MOSFET with lower gate resistance to reduce this effect. If necessary, choose a capacitor value that prevents MOSFET conduction under worst-case temperature and manufacturing conditions. Propagation delay is increased according to the ratio of 1.2 ns/pF. Synchronous MOSFET Enable Under light load conditions, efficiency can be increased by disabling the synchronous MOSFET, thus avoiding the gate charge losses of the synchronous MOSFET. When ENSYNC is low, OUTL is forced low. When high, the low-side driver operates normally. ENSYNC should be driven by a 5-V signal. Shutdown The driver enters shutdown mode when SD is low. Shutdown current is less than 1 mA.
VDD Bypass Capacitor MOSFET drivers draw large peak currents from the supplies when they switch. A local bypass capacitor is required to supply this current and reduce power supply noise. Connect a 1-mF ceramic capacitor as close as practical between the VDD and GND pins. Undervoltage Lockout Undervoltage lockout prevents control of the circuit until the supply voltages reach valid operating levels. The UVLO circuit forces OUTL and OUTH to low when VDD is below its specified voltage. A separate UVLO forces OUTH low when the voltage between BOOT and LX is below the specified voltage.
Thermal Protection If the die temperature rises above 165_C, the thermal protection disables the drivers. The drivers are re-enabled after the die temperature has decreased below 140_C.
TYPICAL CHARACTERISTICS
Highside Turn On Delay vs. CDELAY
50
IDD vs. CLOAD vs. Frequency
140.0 120.0
40
100.0 td(on)H(ns) 200 kHz 80.0 60.0 40.0 20.0 0.0 0 1 2 3 4 5 0 10 20 30 40 50 60 70 80 90 100 110 CDELAY (pF)
IDD (mA)
30 1 MHz 20 500 kHz
10
0 CLOAD (nF)
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Document Number: 72719 S-50265--Rev. C, 21-Feb-05
SIP41105
New Product
TYPICAL WAVEFORMS
Figure 2. PWM Signal vs. LX (Rising) Figure 3. PWM Signal vs. LX (Falling)
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PWM IN 2 V/div
PWM IN 2 V/div
VLX 2 V/div
VLX 2 V/div 50 ns/div
50 ns/div
Figure 4.
PWM Signal vs. HS Gate and LS Gate (Rising)
Figure 5.
PWM Signal vs. HS Gate and LS Gate (Falling)
PWM IN 5 V/div
PWM IN 5 V/div
HS Gate 5 V/div
HS Gate 5 V/div
LS Gate 5 V/div
LS Gate 5 V/div
50 ns/div
50 ns/div
Figure 6.
ENSYNC Delay
ENSYNC 5 V/div HS Gate 5 V/div
LS Gate 5 V/div
50 ms/div Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?72719. Document Number: 72719 S-50265--Rev. C, 21-Feb-05 www.vishay.com
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